1. Field of the Invention
The present invention is concerned with timing circuits. In particular the present invention is concerned with timing circuits configured to generate an output timing signal in dependence on an input timing signal.
2. Description of the Prior Art
It is known to provide a timing circuit which is configured to generate an output timing signal in dependence on an input timing signal. For example within a data processing apparatus an external clock signal may be converted into an internal clock signal for use within a subcomponent of that data processing apparatus. One such example is a self-timed memory system within a data processing apparatus which uses a external clock signal provided by the data processing apparatus to generate a internal clock signal used within the memory system. The memory system is self-timed in the sense that only the leading edge of the external clock is used, the duration of the internal clock pulse being generated in dependence on the requirements of the memory device.
The internal timing of a memory device is known to be a critical operational parameter, since for example when a value read out from the memory device is dependent on the time evolution of the voltage of a bit line, the timing of the moment when that voltage is measured is critical to determining the value that will be read out.
An example of a known timing circuit is schematically illustrated in FIG. 1, wherein an external clock signal CLK is used to generate an internal clock signal ICLK. In the timing circuit 10, the generation of the ICLK pulse is dependent on only the rising edge of the external clock signal CLK. The rising edge of the external clock signal CLK is received by timing circuit 10 via inverter 12 and transmission gate 14. The transition of CLK causes the state held by latch 16 to invert. The resulting rising edge forms the rising edge of the generated ICLK pulse and is also passed via a feedback loop through delay unit 18, the output of which (inverted) controls PMOS transistor 20 which connects the input of latch 16 to VDD. Hence, when the delayed pulse is passed by delay unit 18, the input to latch 16 is pulled high again, causing the state held by latch 16 to invert once more, forming the falling edge of the output pulse ICLK.
However, a problem with timing circuits such as the timing circuit 10 illustrated in FIG. 1 can arise if the timing characteristics of the generated ICLK pulse change over time, since this can affect the performance of a process dependent of the timing of the ICLK pulse. Such changes in the timing characteristics of the ICLK pulse can result from a variation in the switching delay associated with each circuit component of the timing circuit. It is known that each circuit component will exhibit a delay in switching its output level following a transition of its input level. For example inverter 12 illustrated in FIG. 1 will not instantly generate a falling edge when the input CLK signal provides a rising edge, but rather after a finite delay. Since the timing of both the rising edge and the falling edge of the generated ICLK signal are dependent on this switching delay, both the absolute and relative timings of the rising and falling edges of the ICLK pulse are affected by a variation in this switching delay.
Such a variation in the switching delay can, for example, arise when the circuit components of the timing circuit are embodied as silicon-on-insulator (SOI) devices. An example SOI device is schematically illustrated in FIG. 2. The SOI device is formed on a buried oxide layer onto which further layers are laid down to form the transistor components. One characteristic of such a SOI device is that the body of the device is not tied to a reference voltage and is allowed to float. As a consequence the switching delay of a transistor such as that illustrated in FIG. 2 will evolve over time, depending on the initial voltage of the body, eventually settling down to a relatively consistent value, although this may take many switching cycles to occur. An example evolution of the switching delay of a SOI device is illustrated in FIG. 3, in which it can be seen that the SOI device must go through of the order of 10,000 switching cycles before the switching delay settles down to a relatively consistent value.
As mentioned above, the evolution of the switching delay of a circuit component forming part of a timing circuit can have a disadvantageous effect on the timing of the output timing signal generated by the timing circuit and consequently it would be desirable to provide an improved technique for providing timing circuits configured to generate an output timing signal in dependence on an input timing signal.